As the performance of microprocessors improves, there is a growing demand for better performance, higher density memory. Memory manufacturers have addressed this challenge in at least two ways: by developing new types of memory, such as zero-capacitor random access memory (Z-RAM), and by improving the signaling for accessing memory, such as using boosted voltages for accessing SRAM cells. Although these developments helped satisfy the demand for better memory, these developments increased the complexity of memory devices and led to the use of multiple voltage levels in memory devices.
Unfortunately, using multiple voltage levels in memory devices can be expensive in terms of manufacturing cost and power consumption. To use multiple voltage levels, memory devices can either generate the multiple voltage levels on-chip or receive multiple voltage levels from off-chip voltage sources. However, generating multiple voltages on-chip can entail using a charge pump or a tank capacitor, which can consume a large amount of power and die-area. Receiving voltages from off-chip voltage sources can entail dedicating multiple pins for receiving voltages, which can increase the packaging and manufacturing cost.
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with current memory technologies.